During the design of an integrated circuit, a test bench may be used to verify that the design is correct. The test bench may be a simulator that applies stimuli (test vectors) to the inputs of the design and captures responses from the outputs of the design during a simulation. As integrated circuit and application specific integrated circuit (ASIC) designs increase in size and complexity, traditional directed test bench methods to verify the design may be less efficient at finding design errors. A directed test bench generally applies fixed sequences of test vectors to the design under test (DUT) during a simulation. To verify the control path of a DUT, a directed test bench typically is programmed with the exact register access sequence of instructions issued to the DUT via a control command bus.
The register access instruction sequence may vary due to an interrupt routine being started to service an interrupt. Additionally, when multiple functional design units share the same control command bus, the bus traffic may be more complex due to the traffic for various function design units being multiplexed with register access instruction sequences addressed to the DUT. However, generation of all possible test sequences may be a time consuming process when a directed test bench is used. To address some of the shortcomings of a directed test bench, a Constrained Random Test (CRT) test bench may be used. A Constrained Random Test bench architecture may be built on SystemVerilog, a standard language for chip design. SystemVerilog is a unified language for hardware design, specification and verification. SystemVerilog employs register transfer level (RTL) code to describe logic functionality.
What is needed is a constrained random verification methodology focused on the control path of the DUT. What is further needed is an instruction abstraction layer that allows test cases to be created using instructions having a higher level of abstraction. What is also needed is a CRT bench architecture that can randomize valid control oriented test sequences that preserves the validity of the test sequences. What is also needed is a test bench that can randomly insert a noise test sequence and/or an interrupt handling routine into a valid command sequence to test design sensitivity to commands issued outside its address space and/or sensitivity to when an interrupt occurs.